1. Field of the Invention
The present invention generally relates to digital filters and, more particularly, to a Finite Impulse Response (FIR) filter.
2. State of the Art
In conventional practice, computations involved in realizing a FIR filter have been memory access intensive. One data output point of a FIR filter is calculated as ##EQU1## and a succeeding output data point is calculated as ##EQU2## where A.sub.i is one of a series of coefficients defining a windowing function of the filter and X.sub.i is one of a series of input data points.
FIG. 1 shows a known system for performing the foregoing computations. In the system, the coefficients A.sub.i and the input data points X.sub.i are stored in a random access memory 11. The RAM 11 is addressed by an address generator 13 to output corresponding A.sub.i and X.sub.i to a multiplier 15 to form the product A.sub.i X.sub.i. The product A.sub.i X.sub.i is input to either an adder 17 or, in the case i=1, to an accumulator register 19 through a multiplexer 16. When i.noteq.1, the previous sum ##EQU3## stored in the accumulator register 19 is added to the current product A.sub.i X.sub.i in the adder 17 and the cumulative result is stored in the accumulator register 19 through the multiplexer 16. After the sum of the N products has been accumulated in the accumulator register 19, the contents of the accumulator register 19 is output as an output data point. In practice, the coefficients A.sub.i may either be fixed in the case of a non-adaptive filter or may be varied between the calculation of output data points in the case of an adaptive filter.
The system of FIG. 1 requires the address generator 13 to generate 2N addresses per output data point despite the fact that of the 2N operands involved in the calculation, only one of the operands, a new input data point, may differ from the operands involved in the previous calculation. For sophisticated filtering applications, the RAM 11 and its associated address generator 13 normally are so large (in terms of chip area) that they must be located on chips separate from the remainder of the FIR filter circuitry. In such cases, access time for the RAM 11 can be prolonged because of the need to drive the longer interconnect lines. For real-time applications, overcoming these delays requires the use of fast, expensive, and power-hungry logic.